1. Field of the Invention
The present invention relates to an improvement in a liquid crystal display driver for driving a liquid crystal display.
2. Description of the Related Art
The related art will be explained by taking a digital driving source driver for a TFT liquid crystal display as an example.
FIG. 2 is a diagram showing a TFT liquid crystal display 21, as well as a gate driver IC 22 and a source driver IC 23 which are the driver for the liquid crystal display. Each picture element of the TFT liquid crystal display 21 consists of a TFT (MOSFET) 211 and a liquid crystal element 212. The gate driver IC 22 sequentially outputs phase shifted gate driving pulses G.sub.1, . . . , G.sub.M. In addition, the source driver IC 23 (8 gradation display) time divisionally (alternately) outputs to output terminals O.sub.1, . . . , O.sub.N one or two potentials selected from reference voltage V.sub.0, V.sub.2, V.sub.5 and V.sub.7 (being supplied from outside through terminals T.sub.0, T.sub.2, T.sub.5 and T.sub.7, respectively) according to display data D.sub.0, D.sub.1 and D.sub.2 input from a display controller (not shown).
FIG. 3 shows an internal arrangement of the source driver IC 23. The circuit of FIG. 3 is a section corresponding to one output terminal, and the source driver IC has N similar circuits in parallel therein.
D.sub.0, D.sub.1, and D.sub.2 are display data; DM.sub.0, DM.sub.1, and DM.sub.2 are memory circuits which take in display data at timing of clock signal SRi (i=1, . . . , N) and store them; DL.sub.0, DL.sub.1 , and DL.sub.2 are display latch circuits latching the output of a data memory circuit at the timing of horizontal synchronizing signal LS; V.sub.0, V.sub.2 , V.sub.5 and V.sub.7 are reference power supplies; L.sub.0, L.sub.2, L.sub.5 and L.sub.7 are supply lines of the reference power supplies V.sub.0, V.sub.2 , V.sub.5 and V.sub.7, respectively, AS.sub.0, AS.sub.2, AS.sub.5 and AS.sub.7 are analog switches inserted in respective power supply lines, Di is a decoder circuit which outputs signals CAS.sub.0, CAS.sub.2, CAS.sub.5 and CAS.sub.7 for controlling opening or closing of the analog switches AS.sub.0, AS.sub.2, AS.sub.5 and AS.sub.7 based on the outputs of the display latch circuits DL.sub.0, DL.sub.1, and DL.sub.2, and a signal Duty with a duty ratio 1:2; and Oi is an output. The clock signals SRi are sequentially phase shifted timing signals output from a shift register contained in the source driver IC.
The waveform of the signal Duty with duty ratio 1:2 and its generator circuit are shown in FIGS. 4 and 5, respectively.
CK shown in FIG. 4 is a base clock. As shown in FIG. 5, the signal Duty is generated from the base clock CK and the horizontal synchronizing signal LS by using three D-type flip-flops FF.sub.1, FF.sub.2 and FF.sub.3. The generator circuit for the signal Duty with duty ratio 1:2 is provided in the source driver IC. The relationship between the input display data D.sub.2, D.sub.1 and D.sub.0, the output signals CAS.sub.0, CAS.sub.2, CAS.sub.5 and CAS.sub.7 of the decoder circuit Di, and output voltage values is shown in 1 below.
TABLE 1 ______________________________________ Output D.sub.2 D.sub.1 D.sub.0 CAS.sub.0 CAS.sub.2 CAS.sub.5 CAS.sub.7 value ______________________________________ 0 0 0 1 0 0 0 V.sub.0 0 0 1 Duty Duty 0 0 V.sub.0 + 2 .multidot. V.sub.2 3 3 0 1 0 0 1 0 0 V.sub.2 0 1 1 0 Duty Duty 0 2 .multidot. V.sub.2 + V.sub.5 5 3 1 0 0 0 Duty Duty 0 V.sub.2 + 2 .multidot. V.sub.5 . 3 1 0 1 0 0 1 0 V.sub.5 1 1 0 0 0 Duty Duty 2 .multidot. V.sub.5 + V.sub.7 7 3 1 1 1 0 0 0 1 V.sub.7 ______________________________________
FIG. 6 shows an example of arrangement of the decoder circuit Di. It consists of a logical gate which generates and outputs the analog switch control signals CAS.sub.0, . . . listed in Table 1 based on the signal Duty with duty ratio 1:2 and the display data D.sub.0, . . .
In addition, FIG. 7 shows an example of arrangement of the analog switch AS.sub.0 and the like. Although the example of FIG. 7 is constituted by a CMOS transfer gate, it may be constituted by a transfer gate consisting of only a single channel MOS transistor for the channel not causing a threshold voltage drop. For example, AS.sub.0, AS.sub.2 and AS.sub.5 may be constituted only by N-channel MOS transistors. In addition, AS.sub.2, AS.sub.5 and AS.sub.7 may be constituted only by P-channel MOS transistors, by inverting the decoder output.
Now, the operation of the circuit in FIG. 3 will be explained by referring to a timing chart shown in FIG. 8.
As shown in FIG. 8, when the clock signal SRi controlling the data memory circuits DM.sub.0, . . . is at a high level, 3-bit display data D.sub.0, D.sub.1, and D.sub.2 are taken in the memory circuits, output from Q output as they are, and introduced to the display latch circuit DL.sub.0, . . . When the signal SRi falls from the high level to a low level, the data memory circuits maintain the values of D.sub.0 -D.sub.2, and each does not change its Q output even if the input display data D.sub.0 -D.sub.2 change during the interval when the signal SRi is at the low level. Then, when the horizontal synchronizing signal LS controlling the display latch circuits DL.sub.0, . . . is at the high level, the Q output of each of the data memory circuits DM.sub.0, . . . is introduced to the Q output of the display latch circuit DL.sub.0, . . . as it is. When the signal LS falls from the high level to the low level, the Q output of the display latch circuit holds the data of Q output of the data memory circuit at the moment. In addition, during the interval when the signal LS is at the low level, the Q output of each of the display latch circuit does not change even if the Q output of the data memory circuit changes. The Q output of the data latch circuits DL.sub.0, . . . is introduced to the input of the decoder circuit Di. The decoder circuit Di outputs the analog switch control signal CAS.sub.0, . . . as listed in Table 1 according to the content of input. For example, when D.sub.2, D.sub.1 and Do are "1000, " the decoder circuit outputs a signal to turn on only the analog switch AS.sub.0. This outputs the potential of the reference power supply V.sub.0 at the output Oi which is supplied to the liquid crystal display. When D.sub.2, D.sub.1 and D.sub.0 are "011," it outputs a signal which turns on the analog switch AS.sub.2 for a duration of 2/3, turns off the analog switch AS.sub.2 for a subsequent duration of 1/3 to turn on the analog switch AS.sub.5, and alternately repeats this sequence. Thus, the potentials of reference power supplies V.sub.2 and V.sub.5 are alternately output to the output Oi in a temporal relationship of 2:1, and supplied to the liquid crystal display.
In FIG. 2, if, for example, the gate driver 22 is outputting the gate drive pulse G.sub.1, the outputs O.sub.1, . . . from the source driver 23 are applied to respective liquid crystal elements 212, . . . as DC voltage under a low pass filter effect according to wiring resistance of the source lines SL.sub.1, . . . in the liquid crystal display 21, ON resistance of TFTs 211, . . . and wiring capacity of lines SL.sub.1, . . . The voltage once applied to the respective liquid crystal elements is maintained by the capacity of liquid crystal element themselves. Similar operation is repeated every time when the gate drive pulses G.sub.2, . . . , G.sub.M are output, and, after the gate drive pulse G.sub.M is output, the gate drive pulse G.sub.1 is again output to repeat the similar operation.
It has been strongly demanded for battery-driven portable equipment such as a liquid crystal display to further extend the battery operation time, and to further reduce power consumption. For example, in a color TFT liquid crystal panel for a notebook personal computer, because 4 watts out of 6 watts are consumed by a backlight, and a remaining 2 watts are consumed by a liquid crystal driver or the like, it has been essential to further reduce power consumption.
The conventional liquid crystal display driver as described above time divisionally supplies the potentials of two adjacent reference power supplies to the liquid crystal display in the duty ratio according to the display data, and converts them into DC voltage by utilizing the low pass filter effect from the wiring resistance and wiring capacity of the liquid crystal display. Therefore, conventionally, the analog switches of the liquid crystal display driver are repeatedly turned on and off during one horizontal duration to apply oscillation voltage to the input of the low pass filter, and continues to apply the oscillation voltage even after the desired DC voltage is reached so that more oscillation voltage than necessary would be input. Then, the display quality of the liquid crystal display is improved beyond a range which can be visually observed, but unnecessary consumption current occurs.